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> Courses > ECE 211 >Syllabus |
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Syllabus
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Contents:
Laboratory assignements progress from investigation of the properties
of basic logic gates and flip-flops to the design of arithmetic
and sequential circuits using medium-scale integrated circuit
devices as well as programmaple devices. Take home programming
assignements include VHDL code development and simulation.
Laboratory
exercises include:
Introduction to logic hardware - AND, OR, and NOT gates
Introduction to NAND, NOR and XOR Gates; Design of Multiple-Switch
Lamp Controls
Combinational Logic with Multiplexers and Decoders: Design
of a Full Adder
Binary memory units: SR latch, D and JK flip-flops: Design
of a Ripple Counter
Registers and Counters: Design of Universal Shift register,
Ring counter and BCD counter
Final Design Project (includes VHDL and C programming, design, simulation and implementaion of a complete digital system using programmable logic devices)
Work Expected from Students
Attendance is REQUIRED.
Regular readings of the assigned material.
Regular laboratory exercises (in the S/W and H/W laboratories). Preparation prior to each laboratory session is
NECESSARY.
Regular laboratory reports (typed).
VHDL programming assignments.
Final design project and corresponding oral examination.
One midterm and one final examination (comprehensive).
Computer Usage:
Altera Max +II ver. 10.2 will be used on PCs (Windows platform)
for schematic and VHDL description and simulation of digital circuits.
Hardware Laboratory Usage:
Each laboratory station is
equipped with a digital logic breadboard unit containing a power
supply, timers, switches and indicators, an Altera UP2 educational
board with programmable logic devices, ByteBlasterMV parallel port
download cable, and a PC, running Max + II, connected to a network
printer.
Special Considerations:
In the hardware laboratory, students
work in groups of two but maintain individual laboratory notebooks
and submit individual reports. Individual work and reports are required
for experiments and projects using the Altera Max +II computer aided
design tools as well as the VHDL programming assignments.
Grading- Laboratory Exercises/Reports 30%
- VHDL programming assignments 10%
- Final Design Project 20%
- Midterm Exam 10%
- Final Exam (Comprehensive) 30%
Passing
this course requires a total grade of at least 50%, completion of all laboratory exersices and the final project, and a grade of
at lease 50% in the final exam.
The instructor reserves the right
to make minor changes in the above grade distribution. Moreover,
the instructor reserves the right to adjust borderline grades up
or down based on attendance and class participation.
Course Policies- Grading: Inquiries and disputes about graded
work should be made within one week after it has been handed
back. Only inquiries that clearly explain the complaint
will be considered. Not readable/sloppy work will incur an automatic
20% penalty, if accepted.
- Late Work: All work must always be turned in by the predefined
deadline. Late submissions incur a 20% penalty for each day being
late, up to a maximum of 3 days after which no points will be granted.
All extensions should be arranged with the instructor prior to the
due date. No make-up laboratory exercises and exams, or homework assignments
due date extensions will be granted, unless you can provide a valid excuse.
In the case of foreseen absences (such as approved University travel),
you must contact your instructor prior the related absence date.
- Academic Honesty: You are encouraged to
work and talk with other students about the course material and all related work. However, when writing your
laboratory report, homework assignements, program code and documentation, the work
must be solely your own. Work that has significant overlap with
another one is a violation of Academic Honesty and will be reported
to the Department Council. The instructor may use appropriate
software to check the integrity of a report.
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