TECHNICAL
AREAS
Analog and Mixed-Signal
Test:
Haralampos Stratigopoulos,
TIMA Labs,
[email protected]
Biomedical Devices and Applications
Mohammad Sawan
Ecole Polytechnique de Montreal;
[email protected]
CAD for Low-Power Design
Massimo Poncino,
Politechnico di Torino;
[email protected]
Deep-Submicron Design, EDA,
and Technology:
Vivek De, Intel;
[email protected]
Defect-Based Test:
Adit Singh,
Auburn University;
[email protected]
DFM and Yield:
Anne E. Gattiker,
IBM;
[email protected]
Design-for-Testability
Rubin Parekhji, Teaxs Instruments (India);
[email protected]
Economics of Design
and Test:
Magdy Abadir,
Freescale Semiconductor;
[email protected]
Embedded Real-Time Systems:
Prabhat Mishra, University
of Florida;
[email protected]
Emerging Technologies (Bio & Nano):
Mircea Stan,
University of Virginia;
[email protected]
Cyber-Physical Systems:
Paul Bodgan, USC;
[email protected]
Hardware Trust and Secure
ICs:
Ramesh Karri,
NYU Polytechnic School of Engineering;
[email protected]
Interconnect Technologies:
Partha Pratim Pande, Washington State University;
[email protected]
Low Power Systems and Green Computing:
Anand Raghunathan,
Purdue University;
[email protected]
Memory Design and Test:
Cheng-Wen Wu, National Tsing Hua
University;
[email protected]
Said Hamdioui, TU Delft, Netherlands
[email protected]
MultiCore for High Performance and Ultra-Low Power:
David Atienza
EPFL;
[email protected]
Networks on Chip:
Umit Ogras,
Arizona State University;
[email protected]
Online Test and Fault Tolerance:
Qiang Xu,
Chinese University of
Hong Kong;
[email protected]
Physical Design Automation:
Sung Kyu Lim, Georgia Tech;
[email protected]
Reconfigurable Embedded
Systems:
Jan Madsen,
Technical University of Denmark;
[email protected]
Silicon Debug:
Nicola Nicolici,
McMaster University;
[email protected]
SoC Testing:
Erik Jan Marinissen, IMEC;
[email protected]
Asynchronous Design:
Steven Nowick, Columbia University;
[email protected]
System-Level Design and Optimization
Petru Eles
Linkoping University;
[email protected]
Digital and Mixed-Signal Verification, Post Silicon
Validation:
Shobha Vadusevan, UIUC;
[email protected]
Reliable, Secure, and Energy-Efficient Design:
Sanghamitra Roy, Utah State University;
[email protected]
|
DEPARTMENTS
Book
Reviews:
Scott
Davidson,
Oracle,
[email protected];
Grant
Martin, Tensilica,
[email protected];
Igor Markov,
University of Michigan,
[email protected]
CEDA
Currents:
Rajesh K.
Gupta,
University
of California, San Diego;
[email protected]
Reports and
Summaries:
Yervant
Zorian,
Synopsys;
[email protected]
DATC
Newsletter:
Joe Damore,
[email protected]
Interviews:
Erik Jan
Marinissen, IMEC
[email protected]
The Last
Byte:
Scott
Davidson,
Oracle;
[email protected]
Perspectives:
Rajesh K.
Gupta,
University
of California, San Diego,
[email protected];
Yervant
Zorian, Synopsys,
[email protected]
The Road
Ahead:
Andrew Kahng,
University of California,
San Diego; [email protected]
Roundtables:
David Yeh,
SRC;
[email protected]
Standards
(Design):
Stan
Krolikoski, Cadence Design
Systems;
[email protected]
Standards
(Test):
Bill Eklow,
Cisco;
[email protected]
TTTC
Newsletter:
Theo
Theocharides, University of Cyprus;
[email protected]
Tutorials:
Dimitris
Gizopoulos,
University of Athens;
[email protected]
General
Column Editor:
Theo
Theocharides, University of Cyprus;
[email protected]
D&T Alliance Program
DTAP
chair:
Yervant
Zorian, Synopsys;
[email protected]
Asia:
Hidetoshi
Onodera, Kyoto
University;
[email protected]
DAC:
Andrew
Kahng,
University
of California, San Diego;
[email protected]
DATC:
Joe Damore;
[email protected]
DATE:
Ahmed
Jerraya, CEA-LETI;
[email protected]
Europe:
Bernard
Courtois, TIMA-CMP;
[email protected]
Latin
America:
Ricardo
Reis,
Universidade Federal do Rio
Grande do
Sul;
[email protected]
TTTC:
Michael Nicolaidis
TIMA;
[email protected] |
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